1. Field of the Invention
The present invention relates to a level conversion circuit which is utilized in a PECL (Pseudo-ECL) interface serving as a small amplitude interface etc. to convert a voltage level from a CMOS level to a PECL level.
2. Description of the Prior Art
Conventionally, as the level conversion circuit of this kind, there has been the circuit shown in FIG. 1 for purposes of example. FIG. 1 is a circuit diagram illustrating a configuration of the conventional CMOS-PECL level conversion circuit.
The CMOS-PECL level conversion circuit includes input terminals 101, 102 to which differential signals A, AN (inverted signal of A) at the CMOS level (0 V to 5 V) are applied respectively. A gate of a P channel MOS transistor (referred to as "P-MOS" hereinafter) 103 is connected to the input terminal 102. The P-MOS 103 as well as the P-MOS 104 is also connected between the power source Vdd (5 V) and an output terminal 105.
A gate of a P-MOS 106 is similarly connected to the input terminal 101. The P-MOS 106 together with a P-MOS 107 is connected between the power source Vdd and an output terminal 108. In addition, a power source Vt (3 V) is connected respectively to the output terminals 105, 108 via resistors Rt. The resistors Rt are impedance-matched respectively with characteristic impedances Zt of transmission lines.
Differential signals Z, ZN (inverted signal of Z) at the PECL level (3.3 V to 4.1 V) would be output respectively from the output terminals 105, 108. It will be assumed hereinafter that a current will be defined as Iol when the signals Z, ZN at the PECL level of "L" level are output, and that a current will also be defined as Ioh when the signals Z, ZN at the PECL level of an "H" level are output.
The P-MOS's 104, 107 are always in a normal ON state, and the transistor size (i.e., gate width) of them is so adjusted that the current Iol may flow therethrough. While the transistor size of the P-MOS's 103, 106 is so adjusted that a current Ioh-Iol which being derived by subtracting the current Iol from the current Ioh may flow therethrough when the P-MOS's 103, 106 are turned ON.
When the CMOS level signals A (="L" level), AN (="H" level) are input into the input terminals 101, 102, the P-MOS 103 is turned OFF while the P-MOS 106 is turned ON. Therefore, the current output from the output terminal 105 reaches the Iol, and the PECL level signal Z at an "L" level is thus output. The current output from the output terminal 108 reaches the Ioh, and the PECL level signal ZN at an "H" level is thus output.
On the contrary, when the CMOS level signals A (="H" level), AN (="L" level) are input into the input terminals 101, 102, then in the same manner as above the PECL level signal Z at an "H" level is output from the output terminal 105 while the PECL level signal ZN at an "L" level is output from the output terminal 108.
As discussed before, the CMOS level differential signals may be converted into the PECL level differential signals.
However, in the conventional level conversion circuit as above, since desired output currents and voltages may be determined by the transistor size, there has been such a drawback that an output voltage would be varied significantly when manufacturing processes of LSI's, operational conditions such as power source voltage, temperature, characteristic impedance of the transmission line, etc. are varied.